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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C41202 PI6C41204 PI6C41204A
LVCMOS to LVPECL Driver
Features
* Up to Four LVPECL outputs * * * * * * * Selectable CLK0 or CLK1 inputs LVCMOS or LVTTL input level 30ps max output skew 150ps max part-to-part skew 1.9ns max propagation delay 266 MHz output frequency Packaging (Pb-free & Green available): -14-pin TSSOP - 20-pin TSSOP
Description
PI6C4120x is a high-performance LVCMOS or LVTTL to LVPECL clock buffer. The PI6C41204 is a 4 output version with 2 selectable inputs, pin compatible with ICS8535-01. PI6C41204A is the enhanced version with extra power and ground pins to minimize noise and jitter. The PI6C41202 is similar to the PI6C41204 except it has two outputs.
Block Diagram PI6C41204/A
CLK_EN CLK0 CLK1 0 1 D LE Q Q0 nQ0 Q1 CLK_SEL nQ1 Q2 nQ2 Q3 nQ3
Pin Configuration PI6C41204/A
Vee CLK_EN CK_SEL CLK0 nc/Vee CLK1 nc/Vee nc/Vee nc/Vcc Vcc
1 2 3 4 5 6 7 8 9 10 20 19 18 17
20-Pin
16 15 14 13 12 11
Q0 nQ0 Vcc Q1 nQ1 Q2 nQ2 Vcc Q3 nQ3
Block Diagram PI6C41202
D CLK_EN LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q
Pin Configuration PI6C41202
Vee CLK_EN CK_SEL CLK0 Vee CLK1 Vcc
1 2 3 4 5 6 7 14 13
14-Pin 12
11 10 9 8
Vcc Q0 nQ0 nc Q1 nQ1 Vcc
1
PS8626D
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 1a. Pin Description for PI6C41204
N umbe r
1 2
N a me
Vee C LK _EN P o wer Inp ut
Type
Gro und . P ullup
D e s criptio n
S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level. LVC MO S o r LVTTL clo ck inp ut. LVC MO S o r LVTTL inp ut level. N o C o nnect 3 . 3 V sup p ly LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air.
3 4 6 5, 7, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20
C LK _S EL C LK 0 C LK 1 NC Vcc nQ 3 , Q 3 nQ 2 , Q 2 nQ 1, Q 1 nQ 0 , Q 0
Inp ut Inp ut Inp ut Unused P o wer O utp ut O utp ut O utp ut O utp ut
P ulld o wn P ulld o wn P ulld o wn
Table 1b. Pin Description for PI6C41204A
N umbe r
1, 5, 7, 8 2
N a me
Vee C LK _EN P o wer Inp ut
Type
Gro und . P ullup
D e s criptio n
S ynchro nizing clo ck enab le. When HIGH, clo ck o utp uts fo llo w clo ck inp ut. When LO W, Q are lo w, nQ are high. LVC MO S o r LVTTL inp ut level. C lo ck select inp ut: LO W = C LK 0 , HIGH = C LK 1 LVC MO S o r LVTTL inp ut level LVC MO S o r LVTTL clo ck inp ut. LVC MO S o r LVTTL inp ut level. 3 . 3 V sup p ly LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air. LVP EC L o utp ut p air.
3 4 6 9, 10, 13, 18 11, 12 14, 15 16, 17 19, 20
C LK _S EL C LK 0 C LK 1 Vcc nQ 3 , Q 3 nQ 2 , Q 2 nQ 1, Q 1 nQ 0 , Q 0
Inp ut Inp ut Inp ut P o wer O utp ut O utp ut O utp ut O utp ut
P ulld o wn P ulld o wn P ulld o wn
2
PS8626D
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 1c. Pin Description for PI6C41202
Numbe r 1, 5 Name Vee Power Type Ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL input level. Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS or LVTTL input level. LVCMOS or LVTTL clock input. LVCMOS or LVTTL input level. 3.3V supply LVPECL output pair. LVPECL output pair. De s cription
2
CLK_EN
Input
Pullup
3 4 6 7, 8, 14 9, 10 12, 13
CLK_SEL CLK0 CLK1 Vcc nQ1, Q1 nQ0, Q0
Input Input Input Power Output Output
Pulldown Pulldown Pulldown
Table 2. Pin Characteristics
S y mbo l Pa ra me te r C LK 0 , C LK 1 C IN Inp ut C ap acitance C LK _ EN C LK _ S EL RP ULLUP RP ULLDO WN Inp ut P ullup Resisto r Inp ut P ulld o wn Resisto r 2.7 80 K o hm 80 Te s t Co nditio ns M in. Ty p. 3.2 pF M ax. Units
3
PS8626D
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 3a. Control Input Function Table
Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Se le cte d Source CLK0 CLK1 CLK0 CLK1 Q0 thru Q3* Disabled ; LOW Disabled ; LOW Enabled Enabled Outputs nQ0 thru nQ3* Disabled ; HIGH Disabled ; HIGH Enabled Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in figure1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.
Disabled CLK0, CLK1 CLK_EN
Enabled
nQ0 - nQ3* Q0 - Q3*
Figure 1. CLK_EN Timing Diagram
Table 3b. Clock Input Function Table
Inputs CLK0 or CLK1 0 1 Q0 thru Q3* LOW HIGH Outputs nQ0 thru nQ3* HIGH LOW
Note: *PI6C41204 and PI6C41204A have four differential outputs. Q0 through Q3 and nQ0 through nQ3. PI6C41202 has two differential outputs. Q0 through Q1 and nQ0 through nQ1.
4
PS8626D
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested) Storage Temperature ...................................................................-65C to +150C Ambient Temperature with Power Applied .................................. -40C to +85C Supply Voltage, VCC .................................................................................................. +4.6V Input/Output Voltage ........................................................... -0.5V to VCC + 0.5V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 4a. Operating Conditions (Commercial)
Symbol VCC IEE TA Parame te r Supply Voltage Supply Current Ambient Temperature 0 M in. 3.135 Typ. 3.3 M ax. 3.465 50 70 Units V mA C
Table 4b. LVCMOS/LVTTL DC Characteristics, (VCC = 3.3V 5%, TA = 0C to +70C)
Symbol Parame te r CLK0,CLK1 VIH Input High Voltage CLK_EN CLK_SEL CLK0, CLK1 VIL Input Low Voltage CLK_EN CLK_SEL CLK0,CLK1 CLK_SEL CLK_EN CLK0, CLK1 CLK_SEL CLK_EN VIN = VCC = 3.465V VIN = VCC = 3.465V VIN =0V, VCC = 3.465V VIN =0V, VCC = 3.465V --5 -- 150 Te s t Conditions M in. 2 2 -- 0.3 -- 0.3 Typ. M ax. 3.765 3.765 V 0.8 0.8 150 5 A Units
IIH
Input High Current
IIL
Input Low Current
5
PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 4c. LVPECL DC Characteristics (V CC = 3.3V 5%, TA = 0C to +70C)
S y mbo l VO H VO L VS WIN G Pa ra me te r O utp ut High Vo ltage O utp ut Lo w Vo ltage P eak - to - P eak O utp ut Vo ltage S wing Te s t Co nditio ns N o te 1 N o te 1 M in. VC C - 1 . 4 VC C - 2 . 0 0.6 Ty p. M ax. VC C - 1 . 0 VC C - 1 . 7 0.85 V Units
Note: 1. Outputs terminated with 50ohm to VCC - 2V
Table 5. AC Characteristics, (V CC = 3.3V 5%, TA = 0C to +70C (Note 3)
S ymbo l fMAX tPLH tPHL ts ( o ) ts k ( p p ) tDC tr /tf Pa ra me te r Maximum Inp ut F req uency P ro p agatio n Delay Lo w to High : N o te 4 P ro p agatio n Delay High to Lo w : N o te 4 O utp ut S kew : N o te 5 P a r t to P a r t S k e w : N o te 6 O utp ut Duty C ycle O utp ut Rise / F all time 2 0 % to 8 0 % 48 100 50 VC C to VO X VC C to VO X 1.0 1.0 11 Te s t Co nditio ns M in. Typ. M ax. 266 1.9 ns 1.9 30 ps 150 52 400 % ps Units MHz
Notes: 3. All parameters measured at 266MHz unless noted otherwise. The part does not add jitter. 4. Measured from the VDD/2 point of the input to the differential output crossing point. 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output crossing points differential. 6. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Measured at the output crossing points differential.
6
PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 5a. Operating Conditions (Industrial)
Symbol VCC IEE TA Parame te r Supply Voltage Supply Current Ambient Temperature -40 M in. 3.135 Typ. 3.3 M ax. 3.465 50 85 Units V mA C
Table 5b. LVCMOS/LVTTL DC Characteristics, (VCC = 3.3V 5%, TA = -40C to +85C)
Symbol Parame te r CLK0,CLK1 VIH Input High Voltage CLK_EN CLK_SEL CLK0, CLK1 VIL Input Low Voltage CLK_EN CLK_SEL CLK0,CLK1 CLK_SEL CLK_EN CLK0, CLK1 CLK_SEL CLK_EN VIN = VCC = 3.465V VIN = VCC = 3.465V VIN =0V, VCC = 3.465V VIN =0V, VCC = 3.465V --5 -- 150 Te s t Conditions M in. 2 2 -- 0.3 -- 0.3 Typ. M ax. 3.765 3.765 V 0.8 0.8 150 5 A Units
IIH
Input High Current
IIL
Input Low Current
7
PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Table 5c. LVPECL DC Characteristics (V CC = 3.3V 5%, TA = -40C to +85C)
S y mbo l VO H VO L VS WIN G Pa ra me te r O utp ut High Vo ltage O utp ut Lo w Vo ltage P eak - to - P eak O utp ut Vo ltage S wing Te s t Co nditio ns N o te 1 N o te 1 M in. VC C - 1 . 4 VC C - 2 . 0 0.6 Ty p. M ax. VC C - 1 . 0 VC C - 1 . 7 0.85 V Units
Note: 1. Outputs terminated with 50ohm to VCC - 2V
Table 6. AC Characteristics, (V CC = 3.3V 5%, TA = -40C to +85C, See Note 3)
S ymbo l fMAX tPLH tPHL ts ( o ) ts k ( p p ) tDC tr/tf Pa ra me te r Maximum Inp ut F req uency P ro p agatio n Delay Lo w to High : N o te 4 P ro p agatio n Delay High to Lo w : N o te 4 O utp ut S kew : N o te 5 P a r t to P a r t S k e w : N o te 6 O utp ut Duty C ycle O utp ut Rise / F all time 2 0 % to 8 0 % 45 100 50 VCC to VOX VCC to VOX 1.0 1.0 11 Te s t Co nditio ns M in. Typ. M ax. 266 1.9 ns 1.9 100 ps 150 55 400 % ps Units MHz
Notes: 3. All parameters measured at 266MHz unless noted otherwise. The part does not add jitter. 4. Measured from the VDD/2 point of the input to the differential output crossing point. 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output crossing points differential. 6. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Measured at the output crossing points differential.
8
PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
VCC SCOPE Z = 50-Ohm Qx LVPECL VCC = 2V Z = 50-Ohm nQx 50-Ohm VEE = -1.3V 0.165V 50-Ohm
Figure2. 2-3.3V Output Load Test Circuit
Qx nQx Qy nQy tsk(0)
Figure 3. Output Skew
Part 1
Qx
nQx
Part 2
Qy tsk(0)
Figure 4. Part-to-Part Skew
nQy
80%
80% VSWING
CLK0, CLK1 Q0, Q3 nQ0, nQ3
Clock Inputs and Outputs
20% tR tF
20%
tPD
Figure 6. Propagation Delay
Figure 5. Input and Output Rise and Fall Time
nQ0, nQ3 Q0, Q3
Pulse Width
tPERIOD
odc = tPW
tPERIOD
Figure 7. odc & tPERIOD
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PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Packaging Mechanical: 14-Pin TSSOP (L)
0.0256 typical 0.65
14
1
0.193 0.201 4.90 5.10
0.007 0.012 0.19 0.30
0.169 0.177
0.002 0.05 0.006 0.15
0.047 1.20 max.
4.3 4.5
SEATING PLANE
10
0.45 0.75
0.240 0.264
6.1 6.7
0.018 0.030
PI6C4120x LVCMOS to LVPECL Driver
0.004 0.09 0.008 0.20
PS8626D
05/11/05
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C4120x LVCMOS to LVPECL Driver
Packaging Mechanical: 20-Pin TSSOP (L)
20
.169 .177
4.3 4.5
1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 0.45 0.75 .018 .030
SEATING PLANE
.238 .269 6.1 6.7
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 0.05 .006 0.15
Ordering Information
Ordering Code PI6C41202L PI6C41202LE PI6C41204L PI6C41204LE PI6C41204LI PI6C41204LIE PI6C41204AL PI6C41204ALE Package Code L L L L L L L L Package Type 14-pin1 73-mil TSSOP Pb-free & Green, 14-pin1 73-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP 20-pin 173-mil TSSOP Pb-free & Green, 20-pin 173-mil TSSOP Operating Temperature Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8626D 05/11/05

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